E Connect Jain College of Engineering

How to Go Live Streaming GoogleMeet/WebEx/Zoom on YouTube using OBS

JCE_MBA_M, A & CR - Exchange Ratio - Lec 1

Kilbridge and Wester Method Part 2

18ECL58- HDL LAB - 1

Object Oriented Modeling and Design (Introduction)

DESIGN OF PSC STRUCTURES ANCHORAGE ZONE & END BLOCK 01

GWH MODULE 3.4 WELL HYDRAULICS - COOPER JACOB & CHOW METHOD

JCE CV Quantity Surveying and Contracts management(17CV81) 1.1 Introduction and terminologies

JCE_MBA_M, A & CR - Exchange Ratio - Lec 2

JCE ME Ranked Postional Weights(RPW) Method

Design of counters using SR flip flop

JCE CV Design of Prestressed Concrete elements(17CV82) 1.1 Introduction

JCE CSE 18CS55 - M2_L13 - Project Password Locker Execution by Prof. Amritkumar Tupsoundarya

Simulation of gate level 4:1 mux and writing Testbench in Verilog

AI Controlled Gesture Based Virtual Mouse

JCE EE Sensors and Transducers 17EE662 Nagaraj A

Lecture42 LOGIC SYNTHESIS

AI Controlled Gesture based Virtual Mouse

Lecture 39 Automatic tasks and functions in Verilog HDL

JCE MAT Module-5 L(3) Problems on Sample mean by Shafiqahmed

HDL LAB 4 - 18ECL58 - 8:3 Encoder with and without priority

Kernel and User Level Threads

By-pass factor | Psychrometry & Air conditioning

Module 2 Single phase half wave controlled rectifier with RL load and Freewheeling diode

Lecture36 Generate blocks in Verilog

Module 2 1D correlation and convolution

Lecture45 Logic synthesis and design flow explained with Xilinx Synthesis tool

Lecture31 Zero delay control and Event Based timing control

JCE MAT Module-1 : L(15) Example to find the constant "a" & "b" using Irrotational by Shafiqahmed

2.1.7 Compound stress: Problems

Double line to ground fault with fault impedance

Lecture38 Tasks & Functions used in Verilog/18EC56

Lecture50 Useful System Tasks

Sequence Impedances and Networks of Synchronous Machine

Module 4: 1st Derivation (Aerial Photogrammetry)

Exercise Programs on Files in Python

Delays in Verilog