10x Preparation

ideal and practical voltage , current sources | basics of network | EESL | GATE | ESE | PSU

KCL | basics of network | GATE 2014 SET 1 | ECE

Gray Code, Reflected Code, Cyclic Code, and Unweighted Code | Digital Logic Design Full Course

Hamming Code - Part 1: Message Code Formation | VLSI Interview Preparation

VLSI Interview Questions: Design an Adder/Subtractor Unit with Overflow Detection

source transformation | Balance bridge | KCL | CURRENT DIVIDER RULE | EESL | GATE | ESE | PSU

ISRO 2014 Solutions Electronics | ISRO Scientist / Engineer-SC Electronics Previous Year Paper | Q3

VLSI Interview Prep : 2:1 Mux Implementation using AND-OR and NAND Gates | Crack the Interview!

VLSI Interview Prep: Implementing Basic Gates using 2:1 Mux | Step-by-Step Tutorial

VLSI Interview Questions: Designing a Smart 4-Bit Subtractor Unit with Comparator and Adder

GATE 2020 | DAC | Digital Electronics | ECE | Previous year paper | solutions

Electrical utility 2018 PYQ part 2 | BEE PREVIOUS YEAR VIDEO SOLUTION | EESL

Synchronous vs asynchronous counter | 10x crash course in sequential circuit | DE

ESE | Number System | Digital Electronics | ECE | Previous year paper | solutions | GATE 2021

summery of mesh and node analysis | Rating concepts | Network Theory | EESL | GATE | ESE | PSU

Q66 ISRO 2014 Solutions Electronics | ISRO Scientist / Engineer-SC Electronics Previous Year Paper

VLSI Interview Prep: Mux Size Reduction Technique with a Single Inverter

VLSI Interview Questions: Designing a BCD Adder Circuit Using Binary Adder

Q 5 - Duty cycle | ISRO 2013 Solution | ISRO Electronics Previous Year Paper | ISRO Scientist

VLSI Interview Mastery: Implementing 16x1 Mux with 8:1 Mux and 2:1 Mux | 10x1 Mux with 4x1 Mux

VLSI Interview Questions: Crafting a Smart 9's Complement Circuit Using Binary Adder

Voltage and current source connections | basics of network | EESL | GATE | ESE | PSU

Mastering VLSI Interview Concepts: Full Adder, Full Subtractor, and Majority Function with 4:1 Mux

Q7 | ISRO 2013 Solution Electronics | ISRO Scientist | ISRO Electronics Previous Year Paper

VLSI Interview Question | Absolute Value Circuit for 4-Bit Numbers | digital design circuit

Overlapping Moore Type FSM: Detecting Multiple 1's in Last 3 Samples | VLSI Interview Questions

Mastering VLSI Interviews: Implementing Various Mux Sizes using 2:1 Mux | Advanced Tutorial

VLSI Interview Questions : Counting 1's in a 5-Bit Input | Clever Logic Design Technique

Q61 ISRO 2014 Solutions Electronics | ISRO Scientist / Engineer-SC Electronics Previous Year Paper

Sequence detector | finite state machine | vlsi interview question

Q63 | ISRO 2013 Solution Electronics | ISRO Scientist | ISRO Electronics Previous Year Paper

VLSI Interview Questions | Implementing 16:1 MUX using 5:1 MUX and 5:1 MUX using 2:1 MUX

After EESL exam discussion | cutoff | answer key

DATA INTERPRETATION | APTITUDE | PREVIOUS YEAR QUESTIONS | GATE

Silicon wafer

Q24 | ISRO 2013 Solution Electronics | ISRO Scientist | ISRO Electronics Previous Year Paper

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Q69 | ISRO 2013 Solution Electronics | ISRO Scientist | ISRO Electronics Previous Year Paper