VLSI Gyan

The I2C Protocol

FPGA vs ASIC

System on Chip (SOC)

fpga design flow

Common design mistakes: READ WRITE RACE IN VERILOG

APB PROTOCOL

The Multi cycle Path in VLSI

Concept of False Path

Clock Skew and Jitter

Parity Generator

FIFO DEPTH CALCULATIONS

An Introduction to FIFO

Lint in RTL Design || RTL Linting || Linters

How to use ModelSim from Scratch for simulating a verilog code for Half Adder

Function and Task in Verilog.Difference between the Function and Task

SERIAL IN SERIAL OUT Shift Register Verilog code using Xilinx Vivado tool

Synthesizable Constructs in VLSI

Implementation of Logic Gates using MUX