67 тысяч подписчиков
385 видео
59 - Flip Flop Timing Parameters
M11 - 9 - SPI - Driver
78 - Overview of UART Protocol
M7 - 4 - Thevenin & Norton: Example 2
57 - Traffic Light Controller in Verilog
80 - UART Construction Baud Rate Generator
71 - HDL for Memory Arrays
40 - PWM Design in Verilog
M11 - 3 - SPI Protocol - Multiple-Device Configuration
23 - Describing Code Converters in Verilog
29 - Synchronous, Asynchronous, Set, Reset
42 - Linear Feedback Shift Register LFSR in Verilog
21 - Describing Decoders in Verilog
41 - PWM Application
M1 - 9 - Blocking VS NonBlocking Assignments
83 - UART - Demo (Terminal)
4 - Installing Vivado and Digilent Board Files
M11 - 2 - SPI Protocol - Conceptual Architecture
M12 - 6 - I2C Master Controller Design - Basic Actions
26 - Describing D Latches and D Flip-Flops in Verilog
M10 - 3 - PWM - Basic Design
32 - Asynchronous VS Synchronous Counters
60 - Metastability and Synchronizers
27 - Blocking and Nonblocking Assignment
22 - Describing Encoders in Verilog
62 - Sequential Circuits Timing Analysis
30 - Describing Registers in Verilog
M1 - 4 - always Block
M18 - 2 - Frame Buffer Pixel Generation Circuit
19 - Describing Multiplexers in Verilog
5 - End-to-End FPGA Project on the Nexys A7
9 - Hierarchical Design
36 - Counters as Timers
63 - Vivado's Timing Reports
7 - Verilog Primer - Structural Representation
M18 - 3 - Frame Buffer Core
M11 - 5 - SPI Protocol - Operation Modes
49 - Verilog Description of FSMs
12 - Generic Verilog Code Parameterization
M3 - 1 - FSM Review
70 - Artix - 7 FPGA Resources
M15 - 5 - Video IP Core - Architecture
67 - Memory Arrays
