How to design NAND gate simulation using CMOS inverter in PSPice
NAND gate circuit consists of two series NMOS transistors between Y and Ground and two parallel PMOS transistors between Y and VDD.
If either input A or B is logic 0, at least one of the NMOS transistors will be OFF, breaking the path from Y to Ground. But at least one of the pMOS transistors will be ON, creating a path from Y to VDD.
Hence, the output Y will be high. If both inputs are high, both of the nMOS transistors will be ON and both of the pMOS transistors will be OFF. Hence, the output will be logic low.
Subscribe to our channel here: / wasimiqbal1919