Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model.
#Full #Adder/#Subtractor 8 #bit #Code with #Overflow in #Verilog and #VHDL with #Testbench. #Structural #Model.
SV RTL code:
module xor_1(s, a, b);
output s;
input a,b;
assign s = a ^ b;
endmodule // xor_1
module adder_8(s, co, ofl, a, b, ci);
output [7:0] s;
output co, ofl;
input [7:0] a, b;
input ci;
assign s = a + b + ci;
assign co = (a[7] & b[7])|(a[7] & ~s[7])|(b[7] & ~s[7]);
assign ofl = (a[7] & b[7] & ~s[7])|(~a[7] & ~b[7] &s[7]);
endmodule // adder_8
module addsub_8(s, co, ofl, a, b, sub);
output [7:0] s;
output co, ofl;
input [7:0] a, b;
input sub;
wire [7:0] xb;
//assign xb = {8{sub}} ^ b ;//same as above for loop
generate
for (genvar i = 0 ; i ＜= 7 ; i = i + 1) begin
//assign xb [i] = sub ^ b [i] ;
xor_1 myxor(xb[i], b[i], sub);
end
endgenerate
//assign {co, s} = a + xb + sub;
//assign ofl = (a[7] & xb[7] & ~s[7])|(~a[7] & ~xb[7] &s[7]);
adder_8 myadder(s, co, ofl, a, xb, sub);
endmodule // addsub_8
SV RTL testbench:
// test bench of addsub_8
module test_bench;
// 1. Declare testbench variables
reg [7:0] a;
reg [7:0] b;
reg sub;
wire [7:0] s;
wire co, ofl;
integer i;
// 2. Instantiate the design and connect to testbench variables
addsub_8 fa0 (s, co, ofl, a, b, sub);
// 3. Provide stimulus to test the design
initial begin
a ＜= 0;
b ＜= 4;
sub ＜= 0;
// Use a for loop to apply random values to the input
for (i = 0; i ＜ 5; i = i+1) begin
#10 a ＜= $random;
b ＜= $random;
sub ＜= $random;
end
#10;
a = 8'hF6;
b = 8'h0A;
sub ＜= 0;
end
endmodule
VHDL RTL code:
-- to use /* */ enable vhdl 2008 in properties
library ieee;
use ieee.std_logic_1164.all;
entity xor_1 is
port ( s: out std_logic;
a: in std_logic;
b: in std_logic);
end xor_1;
architecture str of xor_1 is
begin
s＜=a xor B;
end str;
-- behavioral model adder 8 bit
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; -- for conv_std_logic_vector
entity adder_8 is
port ( s: inout std_logic_vector(7 downto 0);--use inout if using vhdl 2002
co: inout std_logic;
ofl: out std_logic;
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0);
ci:in std_logic);
end adder_8;
architecture behav of adder_8 is
signal Result : std_logic_vector(8 downto 0);
begin
s ＜= a + b + ci;
co ＜= (a(7) and b(7))or(a(7) and not s(7)) or(b(7) and not s(7));
ofl ＜= (a(7) and b(7) and not s(7)) or
(not a(7) and not b(7) and s(7));
end behav;
--structural model addition/subtraction unit
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; --- conv_std_logic_vector
entity addsub_8 is
port ( s: inout std_logic_vector(7 downto 0);
co: inout std_logic;
ofl: out std_logic;
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0);
sub:in std_logic);
end addsub_8;
architecture struct of addsub_8 is
component adder_8 is
port ( s: inout std_logic_vector(7 downto 0);
co: inout std_logic;
ofl: out std_logic;
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0);
ci:in std_logic);
end component;
component xor_1 is
port ( s: out std_logic;
a: in std_logic;
b: in std_logic);
end component;
signal xb:std_logic_vector(7 downto 0);
begin
--xb ＜= b xor (sub & sub & sub & sub & sub & sub & sub & sub);
xors:for i in 0 to 7 generate
--xb(i) ＜= b(i) xor sub;
myxor:xor_1 port map(xb(i), sub, b(i));
end generate;
-- s ＜= a + xb + sub;
-- co ＜= (a(7) and xb(7))or(a(7) and not s(7)) or(xb(7) and not s(7));
-- ofl ＜= (a(7) and xb(7) and not s(7))
-- or(not a(7) and not xb(7) and s(7));
myadder: adder_8 port map(s, co, ofl, a, xb, sub);
end struct;