Simulating and downloading Counters to Xilinx FPGAs using Schematic design
In this video tutorial our circuits are counters. The counter is a widely used sequential logic, where the output depends on the sequence of past inputs and a present value of the input signals.
In the case of a counter, the input signal is the clock, and the output value represents a number.
The counter circuit is usually built up with flip-flops.
Our first example, a binary up counter.
The counter is constructed from four, rising edge sensitive D flip-flops counting from 0 to 15. Flip-flops store the count until the next event, when the clock signal produces a low to high transition. When the clock is changing low to high the indicator turns red, then the least significant flip-flop, U1, will toggle, and this effect propagates through each flip-flop. This ripple phenomenon causes a delay in the nanosecond domain, but if we don’t care about an immediate result, short transients are acceptable.
To test our circuit in a real FPGA environment we will use a Digilent BASYS3 FPGA board.
Since the board doesn’t provide a 1Hz clock, we have to apply a prescaler which will produce that from the BASYS3 100MHz oscillator.
A counter can count not only a series of pulses, but other events too. For example, the number of times a push button has been pressed
We will go back to our original circuit, and replace the clock source with a push button.
Let the push button (PB) generate a high level when it is pressed and a low level when it is at rest.
The low level needs a resistor.
When the button is pressed, a rising edge occurs on the clock input of the first flip-flop, and the counter outputs will produce the next binary code.
Thus, it will work the same way as the button does on the BASYS3 board.
The mechanical switches and push buttons have contact bouncing problems. If we press a button once in the real world, that may generate a series of pulses. That’s why we place a contact debouncing VHDL macro at the counter input.