Behavioral Modeling | #13 | Verilog in English | VLSI Point
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Structured Procedure
Verilog supports two structured procedure statements always and initial
All behavioral statements are written inside these blocks. These blocks run in parallel i.e. concurrent in nature. Their activity starts at 0 simulation time Blocks cannot be nested.
Procedural Assignment
Procedural assignments update values of reg, integer, real, or time variables. The value placed on a variable will remain unchanged until another procedural assignment updates the variable with a different value.
These are unlike continuous assignments
2 types of procedural assignment:
1. Blocking Assignments
2. Non-blocking Assignments
Delays in Procedural Assignments
Delay-based timing control in an expression specifies the time duration between when the statement is encountered and when it is executed.
1. Regular delay
2. Intra-assignment Delay
Looping Constructs
There are four types of looping statements in Verilog:
for loop
while loop
repeat loop
Forever loop
The syntax of these loops is very similar to the syntax of loops in the C programming language. All looping statements can appear only inside an initial or always block. Loops may contain delay expressions.
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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar
link- https://share.google/6AWAxTsO1z8BspTTF