NAND Logic Gate | NAND is a universal logic gate | A complete explanation with desigining | EG
About this video:-
In this video basically i covered the second part of logic gate that means #universal_logic_gates #NOR_Gate so i discussed the all fundamental concepts of NOR gate as well as designing of NOR gate so i hope you will enjoy the video and there are so many quary regarding this topic:-
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Digital Electronics Syllabus:-
Chapter 1:-Number System, Types of Number System, Decimal Number System, Binary Number System, Octal Number system, Hexa-Decimal Number System Conversion of Number System, BCD(Binary Coaded Decimal), Gray Coad, Conversion of BCD to Gray Code, Conversion of Gray Code to BCD, Excess-3 Code, Compliments, Types of Compliment, Binary Compliment, 0’s Compliment, 1’s Compliment, Decimal Compliment, 9’s Compliment, 10’s Compliment, Octal Compliment , 7’s Compliment, 8’s Compliment, Hexa Compliment, 15’s Compliment, 16’s Compliment,
Chapter 2:- Basics of logic gates, Types of logic gates, Basics Logic Gates, And Gate, OR Gate, NOT Gate, Universal Logic Gates , NAND Gate, NOR Gate, Special Purpose Logic Gates, Ex-OR Gate, Ex-NOR Gate, Switching Circuit, Switching Circuit of Basics Logic Gates, Switching Circuit of AND & OR & NOT Gates, Switching Circuit of Universal Logic Gates, Switching Circuit of NAND & NOR Gate, Switching Circuit of Special Purpose Gate, Switching Circuit of EX-OR & EX-NOR Gate, Truth Table of Logic Gates, Truth table of Basics Logic Gates, Truth table of AND & OR & NOT & NAND & NOR & EX-OR & EX-NOR Gates,
Chapter 3:- Boolean Algebra, Basics Laws/Properties of Boolean Algebra, AND Laws, OR Laws, NOT Laws, Associative Property of Boolean Algebra, Distributive Property of Boolean Algebra, Commutative Property of Boolean Algebra, Demorgans’s theorem, Minimization Technique, Sum of Products(SOP), Products of Sum(POS), Karnaugh Map(K-Map), Grouping of K-Map, Don’t Care Condition, Quine-McCluskey Method, Chapter 4:-Combinational Circuits, Multiplexer, Data Selector,Desigining of Multiplexer, Demultiplexer, 1x2 DMUX,1x4DMUX,1x8DMUX,1x16DMUX, Desigining of Demultiplexer, Decoder, Encoder, Adder, Half-Adder, Full-Adder, Parallel Adder, Desiginig of Adder, Subtractor, Half-Subtractor, Full-Subtractor,
Chapter 5:-Sequential Circuit, Latches, Flip Flop, SR Flip Flop, JK Flip Flop, T Flip Flop, D Flip Flop, Master-slave Flip flop, Application of Flip Flop, Register, Types of Register, Shift Register, Universal Shift Register, Application of Shift Register, Trigger, Clock Pulse, Counter, Counter Designing, Types of Counter, Synchronous Counter, State Diagram of Synchronous Counter, Desiging of Synchronous Counter, Asynchronous Counter, State Diagram of Asynchronous Counter, Types of Asynchronous Counter, MOD UP Asynchronous Counter, MOD Down Asynchronous Counter , Jonshon Counter, Ring Counter, Ripple Counter, Decade Ripple Counter,
Chapter 6:-Semi Conductor Memory, Memory, Memory Organization, Types of Memory, RAM or RWM (Random Access Memory), ROM(Read Only Memory), Internal Organization of Memory, Types of RAM, SRAM, DRAM,
Chapter 7:-Logic family, TTL(Transistor-Transistor Logic), RTL(Resistor-Transistor Logic), DTL(Diode-Transistor Logic), CMOS(Complementary Metal-Oxide Semiconductor) Types of CMOS, N-MOS, P-MOS, Interfacing of CMOS, MOSFET, Buffer,
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