SVAC (System-Verilog-Assertions-Synthesis-Based-Compiler)
The project represents an implementation of an efficient system Verilog Assertions synthesis compiler (SVA-C) that translates the un-synthesizable SVA into synthesizable equivalent Verilog modules. Basically, Assertions have been reported of being an efficient verification and coverage methodology. Being able to synthesis assertions into hardware modules accelerates the time-consuming debug process, which encourages the usage of it as hardware checkers in run time verification approaches; rather than using it in offline environments. Using synthesised assertions in a Runtime verification environment where the design and assertions are placed and kept running on FPGA prototypes gives the privilege of a runtime full visibility of design behaviour, internal signals and more accurate detection of fatal errors. The nature of how assertions are written and designed to cover all specifications rules is what makes assertions more suitable with highly complex SOC which is the main concern of this project to localise potential errors earlier that it is used to. Synthesizing Assertions into hardware opens the way for using the standard SVA language for different purposes, not only hardware checkers but also it can be used to produce triggering or warning circuits of critical high-risk designs. SVA-C has been proved and presented with generic and highly optimised Verilog modules in terms of area performance as our results indicate comparing to other work done.