Digital Control in Switched Mode Power Converters and FPGA Prototyping - NPTEL - Week 8
Problem Solving and Doubt Clearing Session - Week 8
Folder to access Notes - https://drive.google.com/drive/folder...
00:00 - Introduction
03:55 - Q format Representation
07:50 - Addition in Q-format
12:00 - Multiplication of Signed Numbers in Q-format
23:54 - Sample Questions Solved
44:00 - Verilog Code for Digital VMC
1:02:00 - Periodic Step Up and Step Down Transients
1:11:55 - Verilog Code for Generating Transients
1:20:30 - Verilog Code for Clock Generation
1:27:40 - Verilog Code for Digital PID Implementation
1:37:13 - Verilog Code for Mixed Signal CMC
1:38:55 - Current Reference Generation Module Code
1:46:20 - PWM Generation with Dead-time for CMC
1:54:42 - Pulse Skipping Modulation (PSM)
2:05:20 - Verilog Code for PSM Logic