Discussion of a first draft computer design focusing on how the CPU will work.
Course web site with handouts: https://faculty.cs.niu.edu/~winans/CS463
8:27 Memory with 1 write and two read ports (register file)
12:58 Start to see FSM with regs & an ALU
13:26 3-address machine!
16:25 Waveform diagram of regfile & ALU executing instructions
22:50 Surprise!!! An FSM generates waveforms that can control the system!
Show creation of a ROM to generate signals from a counter-addressed MUX
30:30 Add MEM, PC, IR w/horiz encoding indicating the ALU op, reg addresses
39:00 Moore FSM timing diagram to advance PC & control IR & RD_clk
44:29 Sequential insn fetching & decoding!
46:00 Summary of the simple sequential machine
46:30 Add an MAR, MBRI, MBARO, and MUXes o'plenty
Music used in this video (Vibe Tracks, Alternate) was downloaded from the YouTube Audio Library: https://www.youtube.com/audiolibrary_...