Compiler directive & System tasks in Verilog | #14 | Verilog in English

Опубликовано: 09 Октябрь 2024
на канале: VLSI Point

18,309

355

Join our Telegram group for more discussion and get some outstanding materials for exams and interviews along with job/internship opening update : https://t.me/joinchat/9q2ZFEfADY5lZWVl

#vlsipoint #verilog #VLSI #HDL #verilog_in_english
#System_tasks
#Compiler_directives
#Internal_variable_monitoring_system_task
#Simulation_control_tasks
#Simulation_time_related_tasks

System tasks (ST)
1. Internal variable monitoring ST
2. Simulation control Tasks
3. Simulation time related Tasks

There are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($).

1. Internal variable monitoring ST

$display
$write
$strobe
$monitor
$random

2. Simulation control Tasks

$reset
$stop
$finish

3. Simulation time related Tasks

$time
$stime
$realtime

Compiler directives

A compiler directive may be used to control the compilation of a Verilog description. The grave accent mark( ` )denotes a compiler directive.
A directive is effective from the point at which it is declared to the point at which another directive overrides it, even across file boundaries.

`define
`include
`timescale

Don't miss the Verilog videos:

Introduction to HDL | What is HDL? | #1 | Verilog in English
   • Introduction to HDL | What is HDL? | ...

Level of abstraction in Verilog | #2 | Verilog in English
   • Level of abstraction in Verilog | #2 ...

Modules and Instantiation in Verilog | #3 | Verilog in English
   • Modules and Instantiation in Verilog ...

Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in English
   • Simulation, Synthesis and Design meth...

Data types in Verilog | #5 | Introduction | Verilog in Hindi | VLSI Point
   • Data types in Verilog | #5 | Introduc...

Net Data type in Verilog | #6 | Verilog in English | VLSI Point
   • Net Data type in Verilog | #6 | Veril...

Reg Datatype in Verilog | # 7 | Verilog in English | VLSI Point
   • Reg Datatype in Verilog | # 7 | Veril...

Vectors, Arrays, Memories, Parameters, Strings in Verilog | #8 | verilog in English | VLSI Point
   • Vectors, Arrays, Memories, Parameters...

Operators in Verilog | #9 | Verilog in English | VLSI Point
   • Operators In Verilog | #9 | Verilog i...

Practice-Set | #10 | Verilog in English | VLSI Point
   • Practice-Set | #10 | Verilog in Engli...

Gate Level Modeling | #11 | Verilog in English | VLSI Point
   • Gate Level Modeling  | #11 | Verilog ...

Dataflow Modeling | #12 | Verilog in English | VLSI Point
   • Dataflow Modeling | #12 | Verilog in ...

Behavioral Modeling | #13 | Verilog in English | VLSI Point
   • Behavioral Modeling | #13  | Verilog ...

Compiler directive & System tasks in Verilog | #14 | Verilog in English
   • Compiler directive & System tasks in ...

Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar