VLSI Layout - step by step - Rules, Colour Codes, Dimensions of NOT , NOR, NAND Gates
0:00 - A few Layout rules we need - a walk-through
14:30 - How to draw layout of the NOT Gate - step by step
29:20 - Calculating chip area of NOT Gate (27x12 lambda )
33:33 - How to draw layout of NOR Gate - step by step - step by step
1:02 - Calculating chip area of NOR Gate (37x18 lambda)
In above layouts, n-well process is used .
If using p-well, draw a brown box around nMOS transistors at 3 lambda distance from all diffusion.
KTU - EC304 VLSI Syllabus - Module 3