Verilog Sequential Logic Explained: always_ff, always_comb, Latches and FSM Design
0:00 Verilog Sequential Logic Overview — Flip-Flops, Latches, and always Blocks
1:40 Registers in Verilog — always_ff, posedge Clock, and Sensitivity Lists
3:47 Reset Strategies — Synchronous vs Asynchronous Reset (Coding Examples)
6:51 Clock Enable Logic — How Registers Hold State (enable Signal)
9:50 Latches vs Flip-Flops — always_latch and Timing Behavior
12:28 Blocking vs Non-Blocking Assignments — Critical Verilog Coding Rules
13:49 Combinational Logic with always_comb — Case & If Statements
18:01 Priority Encoders and Don’t-Care Logic — casez Usage
20:22 Finite State Machines (FSM) — Moore vs Mealy Models
24:44 FSM Coding in Verilog — enum States, Next-State Logic, Outputs
This lecture builds a complete understanding of sequential logic in Verilog and SystemVerilog, focusing on clean, synthesizable coding style for real digital and VLSI design.
If you already know basic combinational Verilog, this video shows how to model storage elements, registers, latches, and finite-state machines the way professional RTL designers do.
Topics Covered in This Lecture
• The role of sequential logic in digital systems
• Using always_ff for flip-flops and synchronous logic
• Modeling registers with reset, enable, and clocked behavior
• Difference between synchronous and asynchronous reset
• Blocking versus non-blocking assignments and when to use each
• always_comb and always_latch usage rules
• Writing clean combinational logic using if, case, casez
• Priority encoders, decoders, and seven-segment decoders
• Modeling latches correctly and avoiding unintended latch inference
• Introduction to finite-state machine (FSM) design
• Building a divide-by-three FSM example
• Using enums for readable state names
• Next-state logic vs output logic separation
After completing this lecture, you will be able to:
• Write synthesizable sequential logic using modern SystemVerilog constructs
• Understand how hardware registers and latches map to your RTL code
• Avoid common mistakes with blocking and non-blocking assignments
• Implement reliable, readable FSMs suitable for ASIC and FPGA flows
This lecture is ideal for students of digital design, computer architecture, VLSI design, and FPGA development, as well as engineers revising HDL fundamentals for interviews.