Half Adder in Verilog | Testbench + GTKWave | Complete Simulation Tutorial
Welcome to this Verilog tutorial where we implement a Half Adder from scratch using VS Code! In this video, you'll learn how to:
Write a clean Verilog code for a Half Adder
Create a proper testbench to simulate all input combinations
Compile and simulate using Icarus Verilog
View waveforms using GTKWave
Analyze outputs like SUM and CARRY visually
Tools Used:
Visual Studio Code (VS Code)
Icarus Verilog (iverilog)
GTKWave (for waveform visualization)
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