Run Time Verification Methodology Based on SVA with Auto-Correction _Exp. 1
The introduced methodology is a smart but simple approach of incorporating FPGA to facilitate and accelerate verification elements of bug detection and localization, functional checking, and definitely error correction, all on run-time basis. Error detection and localization is the responsibility of Synthesized SystemVerilog Assertions, these were written as a golden-model of the DUT and how it should perform. Correction is performed in an automated way using mutation-based auto-correction mechanism and making use of FPGA dynamic partial reconfiguration technology to keep correcting and testing the running design without stall, which leads to a better time efficiency of the verification cycle.