Software Based Self Test of Embedded Processors
Prime goal of our project is to develop and implement a Software Based Self Testing method of testing and validating embedded microprocessors such as Leon III (Figure 2). The LEON III architecture includes a 7 stages pipelining feature originally from the SPARC V8 architecture, which has been implemented on FPGA (Altera Cyclone). This project deals with the testing of all the segments in the processor with the concept of hardware testing by exploiting the nature of the instruction set. The different stages in the pipeline are explained as follows:
F = Fetch, D=Decode, R=Register access, Ex= Execute, M=Memory, E=Exception, WB= Write-back
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"SBST" technique is an excellent choice for testing the hardware and the motivation rises from the open nature of the LEON III implementation. The whole code base for LEON III is written in VHDL and bares the GPL free software license which is a license for software that respects the user's freedom.
Figure 2: Leon 3 processor architecture
We develop assembly instructions in the form of test patterns or sequences that can be ported onto the target and conduct a rigorous testing on all segments such as the memory, the cache, the intricate pipelining stage, the ALU and the registers. In this project, we will generate/inject our own faults by modifying the VHDL architecture and letting the code generator/software-based self-testing module diagnose the cause of the problem. Our test patterns are going to be much optimized and can test the processors effectively and efficiently by strictly obeying the power and time constraints.
Primarily we will be focusing on developing optimized and smart assembly test patterns that can detect