Implementation of an Efficient Floating-Point Complementor
A short video detailing a few different implementations for an FPGA based floating-point complementor to be used in the VR4300 CPU implementation.
*Update*
I thought of another optimization after making the video, for option 2, the second adder can be explicitly made into a subtractor, and have its bit width reduce to 54 bits to handle double precision floating-point (as opposed to the full 64-bits). Doing so yields better results for the Cyclone V but worse for the Artix-7. It appears to be another case where each device has a more efficient implementation. The results as per the table at the end of the video are:
Cyclone VE Artix-7
LEs FFs FMax(s) FMax(f) LEs FFs FMax(s) FMax(f)
2b | 117 | 196 | 189.7 | 400.3 | 117 | 196 | 225.5 | 377.7
I am not affiliated with any of the companies mentioned in the video. This video is intended for educational purposes.