RISC-V Performance Modeling SIG Presentation February 10, 2023
Talk Description:
RISC-V Performance Modeling SIG, as per its charter, drives development of open-source cycle-accurate performance models of example processor microarchitectures, for use and exploration by the RISC-V community. In this talk, we will introduce Sparta, an event driven framework for micro-architectural simulation and its relevant semantics. Next, we will introduce Olympia, an instruction trace driven cycle accurate performance model of an example out-of-order processor, built using the Sparta framework. We will discuss the current status of the model and future plan of enhancement of the model. Time permitting, we will provide a demo of how the model can be used to do some basic performance analysis.
Speaker bios:
Arup Chakraborty is currently a performance analysis engineer in Ventana Microsystems. His primary area of focus is performance analysis, performance modeling and tools & methodologies used for that purpose. Over the years, working in multiple organizations, he has contributed to analysis and design of CPUs, interconnects, memory subsystems and DDR controllers.
Knute Lingaard is a Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. He is the lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians): a C++/Python project providing discrete event-driven simulation frameworks, performance/analysis tools, and example models. Currently Knute Lingaard is a Performance Architect at SiFive where he contributes to the design/implementation of SiFive high performance CPU designs.
Better version of final video:
• RISC-V Perf-Model: An Open Source Cyc...
Additional interesting URL to a live session on extending RISC-V models:
https://sites.google.com/riscv.org/ri...