Assignment 8: Load and Store Instructions
The RISCV instruction set architecture is based on the concept of a load-store processor architecture. In a load-store system, there are specific instructions that move data from memory to the register file and from the register file to memory while another set of instructions operate on the data only from the register file. With the register file tightly coupled with the processor, it minimizes access (delay) to the data which results in optimal processor frequency or performance.
In this assignment, you will learn how to implement load and store operations in a 5-stage RISCV pipeline as well as overcome a new type of hazard, a structural hazard. A structural hazard in one that results in a pipeline stage not able to complete its operation due to a required resource is not available.
This video is part of Codasip's University Program Assignment 8. It is intended for students who have been assigned a project-based learning assignment, based on the Codasip Curriculum.
All the videos in this assignment are with Keith Graham, Head of Codasip's University Program.
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