FPGA: Lec 1 Create New Project and Simulation in Xilinx Vivado by Anil Sir
This is my first video for Signal Processing with FPGA. In this video, I have created new project in Xilinx Vivado version 2018.1. The created project is simple two bits adder. Once after successfully creation of project, I have also simulated the module for its function verification. In next part-2, you can learn how to elaborate, synthesize and implement the design then finally how to generate bitstream for FPGA programming.