SDRA'22 - 07 - Laurence Barker: RM Processor to Xilinx FPGA Connection for SDR
This presentation describes the interfaces available and work required to support high speed data transfer between Xilinx FPGA and ARM processors for SDR. Zynq FPGAs have both parallel bus interfaces and AXI streams available; other FPGAs can use PCI Express or possibly SPI. Challenges include memory management, cacheing and Linux device drivers. The presentation covers the design decisions made for the "Saturn" SDR with Artix-7 FPGA and Raspberry Pi 4 Compute Module processor, the data rates achieved through various routes and the challenges that had to be overcome. We hope, if all goes well, to show a working Saturn board.
Camera & Edit: FurStreaming
Sebastian Kipp, DL5WN
Marc Diensberg, DO1BOL
Torben Hellige