ALDEC DEMO - UVM Based Environment for Ibex RISC V CPU Core with Google RISC V DV
This presentation showcases the simulation of the Ibex core, which is a 2-stage in-order 32b RISC-V processor core. It has been designed to be small and efficient. The simulation of the SV/UVM testbench for verification of the Ibex core uses Riviera-PRO. This SV/UVM testbench uses the open source RISCV-DV random instruction generator, which generates compiled instruction binaries. We then load these binaries into a simple memory model which then stimulates the Ibex core in Riviera-PRO to run this program in that memory. We then compares the ibex core simulation trace log against a golden model generated by an Instruction Set Simulator (ISS) trace log to check for correctness of execution. The testbench is created based on its usage of the RISCV-DV random instruction generator developed by Google. There are two memory interface agents that are instantiated within the testbench, one for the instruction fetch interface, and the second for the Load-Store Unit (LSU) interface. These agents which run the slave sequences wait for memory requests from the core, and then grant the requests for instructions and data. There is also an Interrupt Interface Agent which is used to drive stimulus onto the Ibex core’s interrupt pins randomly during test execution. The testbench instantiates a single instance of the memory model that it loads the compiled assembly test program into at the beginning of each test. This serves as a unified instruction/data memory that processes all requests from both of the memory interface agents. The tests located in the Tests and Sequence Library are the main sources of external stimulus generation and checking for this testbench, as the memory interface slave sequences simply serve the core’s memory requests.The tests are all extended from core_ibex_base_test, and manage the entire flow for a single test, from loading the compiled assembly binary program into the testbench memory model, to checking the Ibex core status while the test is running and handling test timeouts. The sequences here are used to drive interrupt and debug stimulus into the core.The goal of this testbench is to fully verify the Ibex core with 100% coverage. Riviera-PRO can be used to examine the coverage results, visualize the UVM environment and aide in the debug of the verification environment.