RISC-V Vector Extension Implementation BoF - GNU Tools Cauldron 2018
Presented by Roger Espasa and Graham Markall at GNU Tools Cauldron 2018
The RISC-V Vector Extension has several interesting properties. Two that are particularly interesting from a compiler perspective are:
A hardware vector length that is not only unknown at compile time, but also changes during execution. Changes to the vector length are controlled by software to process as many elements per loop iteration as the hardware can support.
Variable vector unit configuration. The vector register file in any implementation is a fixed size, but the available space can be configured for variable data width and vector length, as well as "type" (scalar, vector, or matrix data). Like the vector length, the configuration is changeable at runtime.
The vector length being determined by the hardware is similar to ARM's Scalable Vector Extensions (SVE), but in SVE the vector length is fixed during program execution. Whilst it is possible to leave the configuration fixed throughout execution in RISC-V, tailoring the vector length and register file configuration will result in higher-performing programs.
This BoF is for discussion about changes to GCC to support the RISC-V Vector Extension and the challenges that it presents, such as the impact on optimizations that the configurable vector length and register file will have.