Creating Macros from Verilog (Hardware Description Languages in TINACloud part 2)
In this tutorial video we will show you how you can create a macro from a Verilog (.v) code and use in TINACloud.
The essential Verilog code of the half adder is 2 lines long only. The Verilog code is much simpler than the equivalent VHDL code. This is one of the great advantages of Verilog.
We will represent how you can turn the uploaded Verilog file into a Verilog macro. and we will also demonstrate how you can Edit the Macro Input and Output pin names.
Finally we will test our newly created macro in TINACloud with digital circuit simulation along with the previously created VHDL macro and compare the results with the Truth Table of the Half Adder.