Verilog Tutorial: Understanding Structural Modeling and Gate Level Modeling | EP-3
In this episode, the viewers are guided through the Verilog Structural Modeling, which involves using gate-level modeling to create digital circuits. The host demonstrates the structural modeling of a Full-Adder using two Half-Adders and a 4-to-1 Mux using Gate Primitives. The episode also covers the writing of test benches for both the Full-Adder and the 4-to-1 Mux using Verilog. The codes are then simulated using two combinations of simulators: Geany IDE + Icarus Verilog + GTK-Wave and Vivado 2022.1 ML Edition. The episode also covers the prerequisites for structural modeling, such as gate primitives, and discusses the differences between Structural and Behavioral Modeling.
____________Download_URL__________________
full-adder.v : https://bit.ly/3Mj1Ve7
mux.v : https://bit.ly/3PYhNWx
___________Installation_Guide_________________
Icarus-Verilog & GTK-Wave Installation in Ubuntu 20.04 LTS : • Why GTK-Wave + Icarus-Verilog are Ess...
Geany-IDE Installation in Ubuntu 20.04 LTS : • Discover Why Geany is Essential for V...
Vivado 2022.1 ML Edition (Windows-10 & Ubuntu 20.04 LTS ) : • Step-by-Step Guide: Installing Vivado...
In this episode we have discussed the below topics :
00:00 Beginning & Intro
00:48 Chapter Index
02:05 Verilog Modelling Methods : Structural & Behavioral Modelling
03:25 Structural Modelling Prerequisites : Gate Primitives
11:16 Structural/Gate Level Modelling : 4 to 1 MUX
17:02 Structural/Gate Level Modelling : 4 to 1 MUX Test-Bench
23:07 Structural/Gate Level Modelling : Full Adder
26:43 Structural/Gate Level Modelling : Full Adder Test-Bench
29:58 Code Simulation : Geany IDE + Icarus Verilog + GTK-Wave
39:34 Code Simulation : Vivado 2022.1 ML Edition
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