PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.
#PC #Program #Counter 8 bit #RTL #Design #Code in #System #Verilog and #VHDL #with #Testbench. #Using #Behavioral #Modeling.
SV PC RTL code:
// PC: program counter
//behavioral model
module P_C(pc, power, clk, branch_pc, branch_en, stop_en, next_pc);
output [7:0] pc, next_pc;
input power, clk, branch_en, stop_en;
input [7:0] branch_pc;
reg [7:0] pc;
wire [7:0] inc_pc, temp_pc0, temp_pc1;
always @(posedge clk)
begin
pc ＜= next_pc; //pc must be reg for this non-blocking assignment
end
// reg [7:0] next_pc;// for use in below always only
// always@(power or stop_en or branch_en or pc)
// //always @(*)
// begin
// if (power)
// begin
// if (stop_en)
// begin
// next_pc = pc;// next_pc must be reg for this
// end
// else
// begin
// if (branch_en)
// next_pc = branch_pc;//blocking
// else
// next_pc = pc + 1;
// end
// end
// else
// next_pc = 8'b0;
// end
// assign next_pc = ~power? 8'b0:
// stop_en? pc:
// branch_en? branch_pc:
// (pc + 1);
assign inc_pc = pc + 1;
assign temp_pc0 = branch_en? branch_pc:inc_pc;
assign temp_pc1 = stop_en? pc:temp_pc0;
assign next_pc = power? temp_pc1: 8'b0;
endmodule // PC
SV RTL testbench:
VHDL PC RTL code:
-- PC: program counter
---- behavioral model
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity P_C is
Port( pc: inout std_logic_vector (7 downto 0);
power : in std_logic;
clk : in std_logic;
branch_pc : in std_logic_vector (7 downto 0);
branch_en : in std_logic;
stop_en : in std_logic;
next_pc: inout std_logic_vector (7 downto 0));
end P_C;
architecture behav of P_C is
signal inc_pc, temp_pc0, temp_pc1 : std_logic_vector(7 downto 0);
begin
process (clk)
begin
if clk'event and clk = '1' then
pc ＜= next_pc;
end if;
end process;
-process(all)- enable vhdl 2008 in properties of file in projext window
--process(power, stop_en, branch_en, pc)
--begin
-- if (power = '1')then
-- if (stop_en = '1')then
-- next_pc ＜= pc;
-- else
-- if (branch_en = '1')then
-- next_pc ＜= branch_pc;
-- else
-- next_pc ＜= pc + 1;
-- end if;
-- end if;
-- else
-- next_pc ＜= x"00";
-- end if;
--end process;
-- next_pc ＜= x"00" when power = '0' else
-- pc when stop_en = '1' else
-- branch_pc when branch_en = '1' else
-- pc + 1;
inc_pc ＜= pc + 1;
temp_pc0 ＜= branch_pc when branch_en = '1' else inc_pc;
temp_pc1 ＜= pc when stop_en = '1' else temp_pc0;
next_pc ＜= temp_pc1 when power = '1' else x"00";
end behav;
VHDL RTL testbench:
---- testbench for PC
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
architecture behav of testbench is
component P_C is
Port( --pc: out std_logic_vector (7 downto 0);
pc: inout std_logic_vector (7 downto 0);
power : in std_logic;
clk : in std_logic;
branch_pc : in std_logic_vector (7 downto 0);
branch_en : in std_logic;
stop_en : in std_logic;
--next_pc: out std_logic_vector (7 downto 0));
next_pc: inout std_logic_vector (7 downto 0));
end component;
signal pc: std_logic_vector ( 7 downto 0);
signal power: std_logic;
signal branch_pc: std_logic_vector (7 downto 0);
signal branch_en: std_logic;
signal next_pc: std_logic_vector(7 downto 0);
signal stop_en: std_logic;
signal clk: std_logic;
begin
uut:P_C port map(pc, power, clk, branch_pc, branch_en, stop_en, next_pc);
clk_Proc: process
begin
clk ＜= '1';wait for 5 ns;
clk ＜= '0'; wait for 5 ns;
end process;
stim_proc:process
begin
power ＜= '0';stop_en ＜= '0';branch_en ＜= '0';
branch_pc ＜= "00000000";
wait for 10 ns;
power ＜= '0';stop_en ＜= '0';branch_en ＜= '1';
branch_pc ＜= "00000001";
wait for 10 ns;
power ＜= '0';stop_en ＜= '1';branch_en ＜= '0';
branch_pc＜="00000010";
wait for 10 ns;
power ＜= '0';stop_en ＜= '1';branch_en ＜= '1';
branch_pc＜="00000011";
wait for 10 ns;
power ＜= '1';stop_en ＜= '0';branch_en ＜= '0';
branch_pc＜="00000100";
wait for 10 ns;
power ＜= '1';stop_en ＜= '0';branch_en ＜= '1';
branch_pc＜="00000101";
wait for 10 ns;
power ＜= '1';stop_en ＜= '1';branch_en ＜= '0';
--branch_pc ＜= "XXXXXXXX";
branch_pc ＜= "00001000";
wait for 10 ns;
power ＜= '1';stop_en ＜= '1';branch_en ＜= '1';
branch_pc ＜= "10000000";
wait for 10 ns;
power ＜= '1';stop_en ＜= '0';branch_en ＜= '1';
branch_pc ＜= "11111111";
wait for 10 ns;
power ＜= '1';stop_en ＜= '0';branch_en ＜= '0';
branch_pc ＜= "01000000";
wait for 10 ns;
wait;
end process;
end behav;