Problem on OPAMP Offset Currents (GATE 2014 ECE Paper Solution) (15th FEB Morning Session)

Functions and Tasks in SystemVerilog with conceptual examples

High Pass RC Circuit as Differentiator and Condition for Good Differentiation

Clocking Regions and why race condition does not exist in SystemVerilog? (23 April 2020)

Solutions to SystemVerilog programs -1 (17th August 2020)

5 Importance of Clocking and Program Blocks, Why Race condition does not exist in SystemVerilog ?

4. Arbiter example with Simple Interfaces & Interfaces with Modports in SystemVerilog

3. Why testing is given more priority? Importance of test-bench and Interfaces

2. Functions and Tasks (call by reference) , automatic keyword, timescale in SystemVerilog

1. Functions & Tasks in System Verilog (call by value )

5. Response of Low pass RC circuit for a Pulse input

6. High Pass RC (HPRC) circuit acts as Differentiator & Condition for perfect differentiation

7. Low Pass RC (LPRC) circut as Integrator and condition for perfect integration

3 .Operation of a Capacitor (How it charges and discharges) PDC JNTU R13

2 Response of LPRC circuit when a sinusoidal input applied - PDC JNTUH R13

1 Pulse & Digital Circuits (PDC) - Introduction to syllabus JNTUH (R13)

4.Bi-directional Diode Sampling Gate - Operation, gain, Vcmin and Vnmin (JNTU PDC)

3.Bi-directional Sampling Gate with provision to remove Pedestal - Operation (JNTU PDC)

2.Emitter Coupled Bi directional Sampling Gates (Pulse & Digital Circuits JNTU)

1.Unidirectional Diode Sampling Gates - Operation, Advantages & Disadvantages (JNTU PDC)

why intrinsic carrier concentration of germanium is larger than silicon ?

GATE 2015 Question paper with Answer Key Civil (8th FEB Forenoon)

GATE 2015 Question paper with Answer Key Mechanical (31st JAN Afternoon)

GATE 2015 ECE Question paper with Answer key - 31st January Forenoon

AC amplifier (Invering and Non-inverting mode) and AC Buffer using OP-AMP - A Conceptual Lecture