Blocking vs Non-Blocking Assignments in Verilog (Shift Register Demo)
Why does your Verilog shift register not work? It is probably the assignment operator. This video demonstrates the critical difference between blocking and non-blocking assignments using a three-flip-flop shift register, showing exactly how blocking assignments destroy sequential behavior by propagating values through in a single clock cycle.
WHAT YOU'LL LEARN:
Why non-blocking is required for sequential circuits and blocking for combinational
How non-blocking assignments update all flip-flops simultaneously at the clock edge
What goes wrong when blocking assignments propagate data through an entire shift register in one cycle
TIMESTAMPS:
0:00 Introduction: two types of equal signs in Verilog
0:15 Blocking vs non-blocking syntax
0:22 The rule: non-blocking for sequential, blocking for combinational
0:38 Shift register example setup with three flip-flops
1:08 Non-blocking demo: correct shift register behavior
2:12 Why non-blocking works: simultaneous assignment
2:19 Switching to blocking example
2:40 Blocking demo: data propagates all the way through
3:05 Explaining the propagation error
3:31 Conclusion: wrong assignment type gives wrong answers
#DigitalLogic #Verilog #Blocking #NonBlocking #ShiftRegister #SequentialCircuits #FPGA #HDL