Implementation of High Speed 8-bit Multiplier in FPGA with Lesser Adder Elements
Implementation of High Speed 8-bit Multiplier in FPGA with Lesser Adder Elements
Abstract
This paper proposes a design method for an 8-bit multiplication with reduced delay time and lesser number of adders. Normally, two numeric data can be multiplied by repeated addition. In the case of binary multiplication, combinational circuit can be designed using manual multiplication method which requires binary addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication. Even though the proposed design is mainly for FPGA implementation, it can also be implemented in ASIC as the logical delay is reduced when compared the result in Xilinx device.
Layman Abstract
This study presents a method for 8-bit binary multiplication that uses multiplexer-based addition to eliminate carry delays. The design increases speed compared to conventional methods and is suitable for both FPGA and ASIC implementation.
Keyword
binary multiplication, carry delay, multiplexer, FPGA, ASIC
Hashtag
#BinaryMultiplication, #FPGA, #ASIC, #DigitalDesign, #HighSpeedComputing
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Source / Reference: https://doi.org/10.9734/bpi/nper/v7/1...