MACRO ..verilog.do PAUSED at line ...Fix Quartus Error: Module '..' does not have a timeunit/timepre
Shows how to #deal and #fix with below #error and #bug in #Quartus prime
Loading altera_ver.dff(fast)
** Error (suppressible): (vsim-3009) [TSCALE] - Module '....' does not have a timeunit/timeprecision specification in effect, but other modules do.
Time: 0 ps Iteration: 0 Instance: /......../uut File: c:/intelfpga_lite/22.1std/questa_fse/win64/../intel/verilog/src/altera_primitives.v
Loading altera_ver.prim_gdff(fast)
Error loading design
Error: Error loading design
Pausing macro execution
MACRO ./......._run_msim_rtl_verilog.do PAUSED at line ....