How to make your ESP32-S3 code faster.
Thanks to https://www.PCBWay.com/?from=atomic for the fantastic PCBs and SMT assembly.
I was trying to squeeze more performance out of an ESP32-S3 and ended up with a result I didn’t expect: optimizing for size was faster than optimizing for speed.
In this video, I benchmark different ESP-IDF settings and show what actually made the biggest difference.
The ESP32-S3 is a seriously capable little CPU, but getting the most out of it isn’t always obvious.
I started with a completely stock ESP-IDF configuration and used a simple but CPU-heavy benchmark: decoding an embedded animated GIF from flash. From there, I measured the impact of a number of common performance tweaks:
• CPU clock speed (160 MHz vs 240 MHz)
• Compiler optimization level (-Os vs -O2)
• Flash SPI mode (DIO vs QIO)
• Instruction and data cache sizes
What surprised me most was that “optimize for size” consistently beat “optimize for performance” in this workload - even before touching the cache settings. Once the caches were increased, the results got even more interesting.
If you’re working on performance-critical ESP32 projects (graphics, codecs, emulation, signal processing), hopefully this gives you a few useful ideas - and maybe challenges a couple of assumptions.
Let me know your findings in the comments!
Thanks for watching!
00:00 The ESP32-S3 and why performance matters
00:36 The benchmark: decoding an embedded GIF
01:03 Baseline results (stock ESP-IDF)
01:43 CPU frequency: 160 MHz vs 240 MHz
02:14 Compiler optimizations: -Os vs -O2
03:32 Flash SPI mode: DIO vs QIO
04:10 Cache configuration (instruction & data cache)
05:08 Turning everything up to 11
05:55 Revisiting -O2 with larger caches
06:14 The winning configuration
06:22 Final thoughts
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