0:00 -- D Latch --
.......................... +--------+
...enable on/off |.........| output
..........set/reset -|........ |
............................+--------+
0:13 enable on (can set/reset output)
0:16 output set
0:18 output reset
0:20 output set
0:23 enable off (can not set/reset output)
0:43 -- 1bit Memory Cell --
.............................+--------+
write/read mode |..........| output
.... access on/off -|..........|
.............set/reset -|..........|
...............................+--------+
0:50 write mode
0:53 access on
0:55 set bit
0:58 reset bit
1:00 set bit
1:03 access off
1:06 read mode
(can not change stored bit)
1:18 access on
(data goes to output)
1:31 (reset to idel state)
1:47 -- 4bit Memory Block --
...(switch) (door)......(switch).......(switches)
....data-in...data-out..write/read...access-address
....|..............|...............|...................||||
....+---------------------------------------------------+
....|........................................................|
1:50 access top left cell
2:05 write mode
2:10 set bit
2:14 read mode
2:21 ('reset bit' does not affect cell during read mode)
2:24 clear access
2:29 (cell is set)
(...)