2 Vivado Execution of 4 BIT MULTIPLIER Verilog + Test Bench Explained With Notes 6th Sem VLSI LAB
PDF : https://sub2unlock.io/A4uSM
VLSI LAB Full Playlist: • VLSI LAB Experiments 6th Sem
VLSI: • VLSI Design and Testing 6th Sem
Embedded Systems: • Embedded System 6th Sem
Time Stamps:
00:00 Syllabus
02:30 4 BIT MULTIPLIER Verilog Code
05:52 4 BIT MULTIPLIER Test Bench Code
08:17 Execution of 4 BIT MULTIPLIER (Procedure)
13:12 Waveform of 4 BIT MULTIPLIER
Your Quries:
✅ Experiments Included:
• 4-bit Adder
• 4-bit Shift and Add Multiplier
• 32-bit ALU using Case & If
• D, SR, JK Flip-Flops
• 4-bit MOD-N Synchronous Counter
• CMOS Inverter – Schematic & Layout
• 2-input NOR Gate – Schematic & Layout
• Boolean Logic Y = AB+CD+E – CMOS Implementation
• Common Source Amplifier – Schematic & Layout
• Two-Stage Operational Amplifier – Full Design Flow
📌 Tools Used: Vivado, Cadence (or equivalent), Simulation, Synthesis, DRC, LVS
💡 Ideal for VTU students, ECE projects, and VLSI learners!