LabVIEW FPGA: Design verification model for the "Reaction Timer" project
Tour of the design verification model (DVM), a desktop VI used to verify the correct operation of the complete reaction timer system.
This video belongs to page http://decibel.ni.com/content/docs/DO... of the series "Digital Circuits and Systems with LabVIEW FPGA" at http://decibel.ni.com/content/docs/DO....