In this video, you learn how to use the HES-DVM partitioning tool to prepare required files for FPGA design prototyping. HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins. HES-DVM™ provides verification teams with multiple use modes including both emulation and physical prototyping techniques enabling SoC teams to work on a single platform.