Building Digital Logic Gates using a 2x1 Multiplexer, AND, OR, NAND, NOR, XOR, XNOR, NOT, BUFFER
In this video I tried to explain in a step by step manner how to build a 2-input digital logic Gate using a 2x1 multiplexer.
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A 2:1 MUX has two data inputs I0I0 and I1I1, one select line SS, and one output YY. The output equation is:
Y=S′⋅I0+S⋅I1Y=S′⋅I0+S⋅I1
Where S′S′ means NOT SS. By fixing I0I0 and I1I1 to constants (0 or 1) or connecting them to a variable, we obtain different gates.
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1. Buffer (Y=AY=A)
Set S=AS=A, I0=0I0=0, I1=1I1=1:
Y=A′⋅0+A⋅1=AY=A′⋅0+A⋅1=A
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2. NOT Gate (Y=A′Y=A′)
Set S=AS=A, I0=1I0=1, I1=0I1=0:
Y=A′⋅1+A⋅0=A′Y=A′⋅1+A⋅0=A′
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3. AND Gate (Y=A⋅BY=A⋅B)
Let S=AS=A, I0=0I0=0, I1=BI1=B:
Y=A′⋅0+A⋅B=A⋅BY=A′⋅0+A⋅B=A⋅B
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4. OR Gate (Y=A+BY=A+B)
Let S=AS=A, I0=BI0=B, I1=1I1=1:
Y=A′⋅B+A⋅1=A′B+A=A+BY=A′⋅B+A⋅1=A′B+A=A+B
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5. NAND Gate (Y=(A⋅B)′Y=(A⋅B)′)
Use AND followed by NOT, or directly:
Set S=AS=A, I0=1I0=1, I1=B′I1=B′:
Y=A′⋅1+A⋅B′=A′+AB′=A′+B′=(AB)′Y=A′⋅1+A⋅B′=A′+AB′=A′+B′=(AB)′
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6. NOR Gate (Y=(A+B)′Y=(A+B)′)
Set S=AS=A, I0=B′I0=B′, I1=0I1=0:
Y=A′⋅B′+A⋅0=A′B′=(A+B)′Y=A′⋅B′+A⋅0=A′B′=(A+B)′
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7. XOR Gate (Y=A⊕BY=A⊕B)
Set S=AS=A, I0=BI0=B, I1=B′I1=B′:
Y=A′⋅B+A⋅B′=A⊕BY=A′⋅B+A⋅B′=A⊕B
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8. XNOR Gate (Y=A⊙BY=A⊙B)
Set S=AS=A, I0=B′I0=B′, I1=BI1=B:
Y=A′⋅B′+A⋅B=A⊙BY=A′⋅B′+A⋅B=A⊙B
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