Downloading Counters to Intel FPGAs in Verilog with TINACloud
In this video tutorial our circuits are counters. The counter is a widely used sequential logic, where the output depends on the sequence of past inputs and a present value of the input signals. In the case of a counter, the input signal is the clock, and the output value represents a number.
The counter circuit is usually built up with flip-flops.
Now, our counter will be based on the Verilog hardware description language.
The textual description of the hardware greatly enhances portability and reusability. Our first example, a binary up counter. The Binary Counter module has the same inputs and outputs as the macro shape. The always block is executed when the clock is rising from low to high or the resetn input falling from high to low.
Instead of implementing a counter with flip flop inference, we increment the q register if the reset is held high and the Clk is rising. Therefore, the counter counts the Clk rising edges.
The q register bit values are assigned to qa, qb, qc, qd respectively. Each output line represents a binary digit.
To test our circuit in a real FPGA environment we will use a Terasic DE10-Lite Intel FPGA board. Since the board doesn’t provide a 1Hz clock, we have to apply a prescaler which will produce that from the DE10-Lite 50 megahertz oscillator. Now let's insert this prescaler as a macro which has been written in VHDL. In TINACloud, we can mix VHDL and Verilog.
A counter can count not only a series of pulses, but other events too. For example, the number of times a push button has been pressed. We will go back to our original circuit, and replace the clock source with a push button. Let the push button (PB) generate a high level when it is pressed and a low level when it is at rest. The low level needs a Resistor. When the button is pressed a rising edge occurs on the clock input of the binary counter module and the counter outputs will produce the next binary code.
Next, we will implement this circuit on an FPGA. Note, that the mechanical switches and push buttons have contact bouncing problems. If we press a button once in the real world that may generate a series of pulses. To debounce the buttons, either FPGA logic or external circuit is necessary. The Terasic FPGA board will eliminate the unwanted glitches by a Schmitt trigger circuit constructing a single low pulse when the button is pressed. Here every time the KEY1 is pressed and released a rising edge is applied to the counter clock input and as a result, it counts up by one.