Programming a Terasic Intel FPGA Board with Schematic Design Entry using TINA
In this video tutorial we will show how to create a digital circuit and download it to a Terasic DE10-Lite FPGA board by using TINA’s Schematic Editor.
The schematic design may contain gates or other built-in digital components in TINA.
In this video, we will use a free Intel tool, Quartus Prime Lite Edition, which is required for the Intel MAX 10 FPGA in the Terasic DE10-Lite board.
First we will test our Half adder circuit in TINA's Schematic Editor with digital circuit simulation.
Before testing our circuit in a real FPGA development board environment, we need to extend our schematic with FPGA Pin connectors.
Next, we need to create the Quartus Prime Lite project to produce downloadable content.
As soon as we finish programming the hardware we can start testing our simulated Half Adder circuit and see how it works along with the programmed DE10-Lite hardware.