RTL Design Engineer Training | Delays and Verilog Event Scheduler | JastTech
Ever wondered why your Verilog testbench prints out outdated, un-updated values, or why your simulation waveform shows the right data but your $display statement says otherwise? Welcome to one of the most critical topics in advanced VLSI verification: The Stratified Event Queue and Simulation Regions.
In this deep-dive lecture, we unpack the mechanics of how hardware simulators manage time-steps and race conditions. We analyze the precise differences between the Active, Inactive, NBA (Non-Blocking Assignment), and Postponed regions. Through concrete coding examples in EDA environments, we demonstrate how Non-Blocking Assignments evaluate their Right-Hand Side (RHS) expressions in the Active region but delay their Left-Hand Side (LHS) updates until the NBA region. You will also learn the behavioral differences between dynamic system tasks like $display, $strobe, and $monitor, proving exactly how simulation scheduler regions alter your debug logs.
📌 Key Concepts Covered:
The Stratified Event Queue: Decoding how a simulator schedules events within a single, distinct time-step.
Active vs. NBA Regions: Understanding why evaluation happens in the Active phase while variable updating stalls until the Non-Blocking Assignment (NBA) phase.
The Role of Inactive Regions: How explicit zero-delay constructs (#0) force simulator events into the Inactive queue.
The Postponed Region Phase: Utilizing $monitor and $strobe to accurately sample stable, post-update values without risking race conditions.
LHS Update Delays: Analyzing why text strings print un-updated or old data during concurrent non-blocking statement execution.
Verification Debugging Methods: Changing value weights live in the compiler to track active scheduling transitions visually.
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