ASIC Flow || Physical Design || VLSI || RTL to GDS Flow
🔧 Complete RTL to GDS Flow Explained | VLSI Design Full Flow
In this video, we walk through the complete RTL to GDS flow — the backbone of modern VLSI chip design. Whether you're a student, fresh graduate, or early-career engineer, this video breaks down every stage of the digital design flow from start to finish.
📌 What's covered:
✅ RTL Design & Functional Verification
✅ Synthesis – RTL to Gate-Level Netlist
✅ Design for Testability (DFT / Scan Insertion)
✅ Floorplanning & Power Planning
✅ Placement
✅ Clock Tree Synthesis (CTS)
✅ Routing
✅ Sign-off – STA, DRC, LVS, ERC
✅ GDS II Tape-Out
By the end of this video, you'll have a solid understanding of how an idea written in RTL (Verilog/VHDL) transforms into a physical layout ready for fabrication.
🎯 Ideal for: VLSI enthusiasts, ECE/EEE students, chip design beginners, and anyone preparing for interviews in the semiconductor industry.
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