Compiler directive & System tasks in Verilog | #14 | Verilog in Hindi

Опубликовано: 14 Июнь 2026
на канале: VLSI Point

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System tasks (ST)
1. Internal variable monitoring ST
2. Simulation control Tasks
3. Simulation time related Tasks

There are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($).

1. Internal variable monitoring ST

$display
$write
$strobe
$monitor
$random

2. Simulation control Tasks

$reset
$stop
$finish

3. Simulation time related Tasks

$time
$stime
$realtime

Compiler directives

A compiler directive may be used to control the compilation of a Verilog description. The grave accent mark( ` )denotes a compiler directive.
A directive is effective from the point at which it is declared to the point at which another directive overrides it, even across file boundaries.

`define
`include
`timescale

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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar
link- https://share.google/6AWAxTsO1z8BspTTF