CASS Talks 2020 - Ney Calazans, PUCRS, Brazil - September 25, 2020
CASS Talks 2020 - September 25, 2020
Facilitating the use of Asynchronous Design: From Dedicated Components to Push-button Circuit Synthesis
Ney Calazans
PUCRS, Brazil
Abstract:
Asynchronous design is not a new subject. Some of the first supercomputers built by humans were designed without ever using clocks. Nonetheless, the evolution of the synchronous design paradigm enabled tremendous advancements in technology, supported by specialized electronic design automation tools. This relegated asynchronous design to a few specialized niches and dedicated researchers that kept the asynchronous flag up. Recent trends such as advanced deep submicron technologies, the deployment of the Internet of Things, extreme low power design requirements and beyond Moore technologies have increasingly challenged the synchronous paradigm. An opportunity to revive asynchronous design is there, but current commercial design tools are not prepared for them, and digital designer education mostly ignores asynchronous techniques. This talk will describe part of the research conducted in the last 15 years by the speaker and his team to enable using asynchronous design. The approach covers from basics such as the design of asynchronous components and cell libraries, through the proposal of asynchronous logic design templates. It ends up with the presentation of a recently proposed push-button flow to design asynchronous digital modules from high level languages such as (System)Verilog and VHDL down to an IP module layout.
Short CV:
Ney Laert Vilar Calazans was born in Maceió, AL, Brazil in 1959. He received a BS-EE degree in 1985 and an MSc-CS degree in 1988 from UFRGS, in Porto Alegre, RS, Brazil. He holds a PhD degree in Applied Sciences (Microelectronics) from the UCL, in Louvain-la-Neuve, Belgium, obtained in 1993. Since 1986 he works at the School of Technology of the PUCRS, in Porto Alegre, RS, Brazil, being a Full Professor there since 1999. In 2014-2015 Prof. Calazans followed a post-doctoral senior stage at the USC in LA, California, USA. His main research interests involve digital design in general, non-synchronous hardware design in particular, networks-on-chip, computer architectures and applications. Prof. Calazans holds a Research Productivity Scholarship (Level 1-C) from the CNPq and is an IEEE senior member. He is also a member of the SBC and SBMICRO Brazilian societies. He is the author or co-author of around 200 publications in scientific journals and conferences, and works as a full member of the Graduate Program in Computer Science (PPGCC) at the PUCRS, where he already advised to completion 31 PhD or MSc thesis/dissertations.