Gate Level Modeling | #11 | Verilog in Hindi | VLSI Point

Опубликовано: 19 Июнь 2026
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Verilog has predefined inbuilt gate primitives. It is the lowest level of abstraction. All logic gates can be implemented using these gates-

1. Basic gates (And/Or , Buf/Not)
2. Bufif/Notif gates

And/Or Gates:

It has One scalar output and multiple scalar inputs. Output of a gate is evaluated as soon as one of the input changes. The and/or gates available in verilog are:

and gate
or gate
xor gate
nand gate
nor gate
xnor gate

Buf/Not Gates:

These gates have one scalar input and one or more scalar outputs.

Bufif/Notif Gates:

These gates have a additional control signal. They propagate if the control signal is given otherwise the output will be in high impedance state.

bufif1
bufif0
notif1
notif0

Gate Delays

In Verilog we can introduce gate delays in the logic circuits.
Three types of delays from input to output of gates-

1. Rise delay
2. Fall delay
3. Turn-off delay

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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar
link- https://share.google/6AWAxTsO1z8BspTTF