SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Model
#SRA #Arithmetic #Shift #Right 8 bit #RTL #Code in #Verilog and #VHDL with #Testbench. #Using #Structural #modeling
SV SRA RTL code:
module mux2to1_8(in0, in1, sel, o);
output [7:0] o;
input [7:0] in0, in1;
input sel;
assign o = sel? in1:in0;//data flow modeling/continuous assignment
endmodule // mux2to1_8
// structural model shift right logic b is 2:0 for sra
module shift_right_arithmetic_8(s, a, b);
output [7:0] s;
input [7:0] a, b;
wire [7:0] s1, s2;
// reg [7:0] s;
// always@(*)
// begin
// if (b[2:0] == 0)
// s = a;
// else if (b[2:0] == 1)
// s = {a[7],a[7:1]};
// else if (b[2:0] == 2)
// s = {a[7],a[7],a[7:2]};
// else if (b[2:0] == 3)
// s = {a[7],a[7],a[7],a[7:3]};
// else if (b[2:0] == 4)
// s = {a[7],a[7],a[7],a[7],a[7:4]};
// else if (b[2:0] == 5)
// s = {a[7],a[7],a[7],a[7],a[7],a[7:5]};
// else if (b[2:0] == 6)
// s = {a[7],a[7],a[7],a[7],a[7],a[7],a[7:6]};
// else if (b[2:0] == 7)
// s = {a[7],a[7],a[7],a[7],a[7],a[7],a[7],a[7]};
// else
// s = 8'hzz;
// end
//assign s1 = b[0] ? {a[7], a[7:1]}: a;
mux2to1_8 mux1(a, {a[7], a[7:1]}, b[0], s1);
//assign s2 = b[1] ? {s1[7], s1[7], s1[7:2]}: s1;
mux2to1_8 mux2(s1, {s1[7], s1[7], s1[7:2]}, b[1], s2);
//assign s = b[2] ? {s2[7], s2[7], s2[7], s2[7], s2[7:4]}: s2;
mux2to1_8 mux4(s2, {s2[7], s2[7], s2[7], s2[7], s2[7:4]}, b[2], s);
//
endmodule // shift_right_arithmetic_8
SV RTL testbench:
// test bench for shift right arithmetic
module testbench;
wire [7:0] s;
reg [7:0] a, b;
integer i;
shift_right_arithmetic_8 sra(s, a, b);
initial begin
#0 a = 8'h00;b = 8'h00;
#10;
for (i = 1;i＜ = 7;i = i + 1)
begin
a = a + 8'h04;
b = b + 8'h01;
#10;
end;
a = 8'hF6;
b = 8'h0A;
end
endmodule
VHDL SRA RTL code:
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1_8 is
port ( in0: in std_logic_vector ( 7 downto 0);
in1: in std_logic_vector (7 downto 0);
sel: in std_logic;
o: out std_logic_vector(7 downto 0));
end mux2to1_8;
architecture str of mux2to1_8 is
begin
o ＜= in1 when sel = '1' else in0;
end str;
----- structural model shift right arithmetic b is only for 2:0 bits for sra
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;-- for to_integer
entity shift_right_arithmetic_8 is
port ( s: out std_logic_vector(7 downto 0);
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0));
end shift_right_arithmetic_8;
architecture beh of shift_right_arithmetic_8 is
component mux2to1_8 is
port ( in0: in std_logic_vector ( 7 downto 0);
in1: in std_logic_vector (7 downto 0);
sel: in std_logic;
o: out std_logic_vector(7 downto 0));
end component;
signal s1, s2: std_logic_vector(7 downto 0);
begin
--Process(all)
--begin
-- if (b(2 downto 0) = "000")then
-- s ＜= a;
-- elsif (b(2 downto 0) = "001")then
-- s ＜= a(7) & a(7 downto 1);
-- elsif (b(2 downto 0) = "010")then
-- s ＜= a(7) & a(7) & a(7 downto 2);
-- elsif (b(2 downto 0) = "011")then
-- s ＜= a(7) & a(7) & a(7) & a(7 downto 3);
-- elsif (b(2 downto 0) = "100")then
-- s ＜= a(7) & a(7) & a(7) & a(7) & a(7 downto 4);
-- elsif (b(2 downto 0) = "101")then
-- s ＜= a(7) & a(7) & a(7) & a(7) & a(7) & a(7 downto 5);
-- elsif (b(2 downto 0) = "110")then
-- s ＜= a(7) & a(7) & a(7) & a(7) & a(7) & a(7) & a(7 downto 6);
-- elsif (b(2 downto 0) = "111")then
-- s ＜= a(7) & a(7) & a(7) & a(7) & a(7) & a(7) & a(7) & a(7) ;
-- else
-- s ＜= x"ZZ";
-- end if;
--end process;
--s1 ＜= a(7) & a(7 downto 1) when b(0) = '1' else a;
mux1:mux2to1_8 port map(a, a(7) & a(7 downto 1), b(0), s1);
--s2 ＜= s1(7) & s1(7) & s1(7 downto 2) when b(1) = '1' else s1;
mux2:mux2to1_8 port map(s1, s1(7) & s1(7) & s1(7 downto 2), b(1), s2);
--s＜= s2(7) & s2(7) & s2(7) & s2(7) & s2(7 downto 4) when b(2) = '1' else s2;
mux4:mux2to1_8 port map(s2, s2(7) & s2(7) & s2(7) & s2(7) & s2(7 downto 4), b(2), s);
end beh;
VHDL RTL testbench:
-- test bench for shift right arithmetic
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity testbench is
end testbench;
architecture beh of testbench is
component shift_right_arithmetic_8 is
port ( s: out std_logic_vector(7 downto 0);
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0));
end component;
signal s,a,b: std_logic_vector( 7 downto 0);
begin
sll8: shift_right_arithmetic_8 port map(s, a, b);
process begin
a ＜= x"00";b ＜= x"00";
wait for 10 ns;
for j in 1 to 7 loop
a ＜= a + x"04";
b ＜= b + x"01";
wait for 10 ns;
end loop;
A ＜= x"F6";
B ＜= x"0A";
wait for 10 ns;
wait;
end process;
end beh;