Timing Constraints in Sequential Synchronous Circuits
This is a tutorial on timing in sequential synchronous circuits composed of edge-triggered flip flops and combinational logic. In this video, I present some timing constraints and show how to ensure that they are satisfied.
Table of contents:
00:00 - Introduction
00:34 - Timing diagrams
03:11 - Flip flop timing
08:35 - Flip flop with feedback
15:48 - Linearization of flip flop paths
17:23 - Flip flop with more complicated feedback
18:52 - More complicated example
24:21 - Conclusion