Phase Locked Loop (PLL) Part 2 on cadence
PLL behavioral modelling using verilogA coding in cadence. The video shows how to make a test bench to check the operation of different PLL blocks using cadence. The test bench of the Phase Frequency Detector (PFD) and its input and output waves at different cases are shown in detail using simulation in cadence.
Please, if anything is not clear, feel free to ask.
Update : Here is the link of my thesis where you can find all the PLL circuit diagrams and detailed explanation of PLLs and frequency synthesizers.
https://www.researchgate.net/publicat...