Algorithms to Architecture, ECE, IIIT Delhi

Lab1_Part_2_2: Verilog based Sequential Design to control PMOD 7-Segment Display on Basys 3 FPGA

Lab1_Part_1_3: Verilog based Sequential Design to control 7-Segment Display on Basys 3 FPGA

Lab_6_Part_2 (FPGA FIFO IP and verification via remote server, ILA/VIO)

IIITD AELD Lab2_P4: SDK Debugging for FFT on Zedboard ARM Cortex A9

IIITD AELD Quiz 1 Gr. 10 Submission: Introduction to AMBA: AHB and APB

Lab1_Part_1_2: Verilog based Sequential Design to control 7-Segment Display on Basys 3 FPGA

IIITD AELD L2_P3: Advanced Micro-controller Bus Architecture (AMBA)

Lab_10_Part_2 (Matrix Multiplication using ARM and Debugging using Vivado SDK)

IIITD AELD Lab6_P2: Zynq SoC Timers/Counter and Interrupts: System Watchdog Timer

IIITD AELD Quiz 1 Gr. 6 Submission: Introduction to AMBA: AHB and APB

Lab_10_Part_1 (Matrix Multiplication using ARM and Debugging using Vivado SDK)

IIITD AELD Lab8_P3: HLS IP with AXI Stream Interface for Matrix Multiplication

Lab_4_Part_1 (FSM using Verilog and Verification on Zybo via ILA, VIO and remote hardware server)

IIITD AELD Lab11_P4: AXI DMA Scatter Gather Mode: Demonstration on Zedboard

IIITD AELD Lab13: FIR Filter Acceleration via AXI DMA Scatter Gather Mode: Demonstration on Zedboard

IIITD AELD Lab11_P2: AXI DMA Scatter Gather Mode: Buffer Descriptors

IIITD AELD Lab11_P1: AXI DMA Scatter Gather Mode and Comparison with AXI Simple DMA

IIITD AELD Lab12: AXI DMA Scatter Gather Mode for Multiple Packets: Demonstration on Zedboard

Lab1_Part_1_4: Verilog based Sequential Design to control 7-Segment Display on Basys 3 FPGA

P4_OFDM on RFSoC Using MATLAB without HDL Coder

IIITD AELD Lab1_P1: Review: Introduction to Vivado and SDK

Lab1_Part_2_1: Verilog based Sequential Design to control PMOD 7-Segment Display on Basys 3 FPGA

IIITD ECE573 AELD: Lab_8_Part_2: Microblaze and GPIO Simulation

Lab_8_Part_2: Introduction to Zynq Design Flow: SDK

Lab_10_Part_4: DMA in Zynq SoC