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Why Folded Cascode OTA?
Why Pseudo-JTOL in a CDR Design or Verification?
Maximizing SoC Bandwidth using Dynamic Voltage and Frequency Scaling in 2021 CSIA ICCAD
Why Equalization?
Why A Dedicated Noise Analysis for A Strong-arm Latch / Comparator?
Why Active CTLE in a high-speed SerDes?
Why PLL?
Why Passive CTLE?
Why Power Integrity (PI) Analysis with Package Model?
Why CMFB in A Fully Differential Amplifier?
Why DVFS?
Why Peaking Gain & BW Tradeoffs in CTLE?
A Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools
Why Transmit Encoded Data to A SerDes Interface?
Why Adaptation in Discrete-time Equalizers?
Why On-die Power Integrity (PI) Analysis w/ IR-drop?
Why A Dedicated DC Offset Calibration for Strong-arm Latch, Pre-amplifier Summer and CTLE?
Why Bang-bang (BB) Loop Dynamic Analysis or Phase Tracking Modeling in a BB CDR Design?
Why DFE?
Why Mueller–Muller CDR in A High-speed SerDes?
Why A Mixed-Signal Verification?
Why Single-ended Signaling in a SerDes?
Why Dynamic Offset or Mismatch Cancellation with Auto-zeroing Technique?
Why Bang-bang Phase Detector in a CDR?
Why Phase Interpolator Based CDR?
Why PLL-based CDR?
